Inflection Phenomenon in Cryogenic MOSFET Behavior

This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the current in weak and moderate inversion at a given gate voltage compared to the drift-diffusion current. This phenomenon is explained by introducing a Gaussian distribution of localized states centered around the band edge. The localized states are attributed to disorder and interface traps. The proposed model allows to extract the density of localized states at the interface from the dc current measurements

Cryogenic MOS Transistor Model

This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to zero Kelvin as a result of dopant freeze-out in cryogenic equilibrium. Explicit MOS transistor expressions are then derived including incomplete dopant-ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependency of the interface-trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on a commercially available 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically-accurate compact models dedicated to low-temperature CMOS circuit simulation.Comment: Submitted to IEEE Transactions on Electron Device

Generalized Boltzmann relations in semiconductors including band tails

Boltzmann relations are widely used in semiconductor physics to express the charge-carrier densities as a function of the Fermi level and temperature. However, these simple exponential relations only apply to sharp band edges of the conduction and valence bands. In this article, we present a generalization of the Boltzmann relations accounting for exponential band tails. To this end, the required Fermi-Dirac integral is first recast as a Gauss hypergeometric function, followed by a suitable transformation of that special function, and a zeroth-order series expansion using the hypergeometric series. This results in simple relations for the electron and hole densities that each involve two exponentials. One exponential depends on the temperature and the other one on the band-tail parameter. The proposed relations tend to the Boltzmann relations if the band-tail parameters tend to zero. This work comes timely for the modeling of classical semiconductor devices at cryogenic temperatures for large-scale quantum computing

Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by measuring a variation of the electric current due to the presence of a magnetic field, in a specific nanowire network topology. This method overcomes the limitations inherent to the standard Hall effect technique and might open the way to a more precise and simple measurement of mobility in nanowires, still a matter of intensive research

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs

Negative Capacitance Tunnel FETs: Experimental Demonstration of Outstanding Simultaneous Boosting of On-current, Transconductance, Overdrive, and Swing

This paper demonstrates and experimentally reports the highest ever performance boosting in strained silicon-nanowire homojunction TFETs with negative capacitance, provided by matched PZT capacitors. Outstanding enhancements of Ion, gm, and overdrive are analyzed and explained by most effective reduction of body factor, m VT, which greatly amplify the control on the surface potential TFET, which dictates a highly non-linear BTBT regime. We achieve a full non-hysteretic negative-capacitance switch configuration, suitable for logic applications, and report on-current increase by a factor of 500x, voltage overdrive of 1V, transconductance increase of up to 5×103x, and subthreshold swing improvement